In the conventional process for forming copper damascene structures in semiconductor devices, after the damascene opening has been etched into the porous low-k interlayer dielectric (ILD), the bottom etch stop layer is etched with a dry etch process before the damascene opening is filled with copper metal. A number of materials may be used for the bottom etch stop layer. Silicon carbide and silicon nitride are examples of materials commonly used for this purpose. Where the bottom etch stop layer is silicon nitride, the dry etch process conventionally practiced is plasma etch with a bias power. However, this etch process is generally conducted with a very low bias power because any “overetch” of the silicon nitride layer will cause undesirable back sputtering of the underlying copper in to the via. Such back sputtering of the underlying copper is not desirable because the sputtered extraneous copper deposits on the sidewalls of the low-k ILD can cause reliability problems.
Thus, an improved method of etching the silicon nitride bottom etch stop layer in a copper damascene structure is desired. The concerns discussed herein are equally applicable to single damascene structures, copper via step structures, and copper dual damascene structures (with or without an intermediate etch stop layer).